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  Pirooz Najafi
Senior Embedded Hardware &
Software Design Engineer
Phone: (469) 229-9010
Fax: (469) 229-9009
Mobile: (214) 335-7183
Email: pirooz@emtecsolution.com
EXPERIENCE HIGHLIGHTS
Strong system, hardware, firmware, software problem solving, troubleshooting
Embedded hardware(PCB, System, Digital, Mixed signal) & software (Realtime)
Experience with Motorola 680x0, PowerPC and PowerQUICC, AMD 2900 Series Bit slice processors, TI TMS320C6000, Motorola 56000, DSP56301, DSP56307
High Performance DSP, Digital Filter design implementation, DTMF, MF, SF, Modem tone detection and generation, SF and N5 international tones, signaling.
Real Time Message processor, DMSY, DMSX, DS30 message protocol, HDLC, LAPD, LAPB, SS7
AMP, CDMA and TDMA cellsite, Billing server, MSC system design and support, Memory Controller design and FPGA, CPLD,PAL development
Time switch, Nortel DMS100, DMS250, Billing server, DMS500, DMS300, MTX, XPM, DTC, ICP, DSPM, ICRM, DTC, PDTC, ENET, ECORE, Danray RSS250, PBX, CTSS4000, CTSS1000 PDSN, Passport, OC3 Express
System experience, System test, PCB test and repair, Nova and Point4 Mini computer interface and memory Maper/banking/ECC expansion design.
EXPERIENCE (Complete List)
Emtec Solution (Embedded Technology System Solution) Plano, TX (2005-present)
Technical Advisor (2005)
Wireless sensor network design, FPGA, CPLD reference design and Eval boards.
Research and development for new product, turn key and customized test and verification systems.
We design and work with our contract manufacture to build the products for our customers.
DALLAS LOGIC, Plano, TX
Contractor for AMIS, Plano, TX (2004-present)
Technical Advisor (2004-2005)
FPGA Hardware and software design and testing Contract from AMIS
DALLAS LOGIC, Plano, TX
Technical Advisor (2004-2005)
FPGA Hardware and software design and testing.
Subcontractor for AMI semiconductor working on 8051 IP Core and its peripheral reference design for the AMIs R8051 ASIC.
Diagnostics and testing using assembly language and C Programs CAST80515, CAST Z80.
Functional and timing simulation and design verification.
RTL design and simulation using verilog, Xilinx and cadence tools.
Self Employed
Technical Advisor (2003)
Research and Marketing for Investment in technology (Home Automation, DSU, Child security in shopping center, Automotive, Telecommunication Test equipment) and financial sector.
Exploring product design possibility with Dallas Logic Inc.
Home Automation/Control cooling. Design In progress working with overseas resources.
T1/E1 DSU to fix/improve existing/new telecommunication equipment in the field.
Children security in Malls and parks.
Low cost/small size T1/E1 Test tools for the lab techs.
Automotive valet parking key and car location locator.
NORTEL NETWORKS, Richardson, TX (1980-2003)
Technical Advisor (2002-2003)
Contributed to design, development, verification and support of CDMA 1XRTT Base Station Controller (BSC) Platform and support of the Cell site (BTS). Maintenance data base configuration for the PDSN. Hardware and software, modification and debugging for:
NT SCIS (L2TP, Messaging, Processor, Ethernet, time switch)
ESEL (DSP, CDMA voice channels, speech coding) software and hardware modification and debugging.
CDMA lab support for interfaces to OC3 and T1/E1 links.
Supported software integration and testing.
CDMA design lab Manager and Technical Advisor (2000-2001 support up to 2003)
Responsible for the CDMA design lab equipments (DMS100, MTX, PBX, BSC, BTS, RF equipments, CDSU, SUN workstations) and staff.
Manage lab tech staff daily assignments.
Scheduled lab resources and communicate system status with the design team
Provided staff feed back for the year end performance review.
Worked with the team to resolve any technical issue with the TDMA and CDMA MSC, BSC, BTS and any test equipments like code test emulators and logic analyzer
Technical Advisor (1993-2000 support up to 2003)
Contributed to design, development, and verification and supported enhanced features for the Nortel TDMA Base Station and Cell site Controller.
Supported the hardware design team for the Processor board with Motorola 68060 and High Speed Memory to achieve required performance. Integration team.
Design and implemented the firmware for the RMTC (Cell site controller, Processor 68040) .
Re-Design and implemented the system timing synchronization software and firmware for the RMTC to fix system timing and reliability issues.
Provided hardware and software design support to the TDMA design team for the MTX, ICP, ICRM, DSPM, TDMA Dual Mode Radio, Enhanced Time switch (Motorola 56xxx DSP, Constant delay time switch, Base station controller, Cell site controller, DSP Module for TDMA vo-coder resource pull, DSP shelf, circuit pack and interface and control design)
DMS-300, DMS-500 International Gateway Switch Design Support (1993)
Technical Advisor working wit the field customer verification team to identify hardware, software and firmware design problem and recommend patches to fix problems and work with designers to propagate the fixes to the source code and schematics.
Worked on computing module, message processor, time switch, trunk controller, tone receivers, tone senders, T1, E1 links, International tones for signaling.
Enhanced Time Switch (1993 support up to 2003)
Technical Advisor for redesign, verification and support for the Enhanced Time Switch Circuit Pack.
Addition of new features to double capacity for the peripheral side time slots.
Enhanced switching capabilities to include peripheral to peripheral switching while preserving end-to-end signaling.
Supported manufacturing introduction and regulatory testing.
Design and Implement DTC time slot monitoring tools built into the time switch circuit pack to assist designers for detecting and debugging filed issues (Using Altera EPLD).
ICP, DSPM Team Leader (1988-1992 support up to 2003)
Responsible for design, development, verification, introduction and support for ICP T1/E1 Time Switch for the Nortel TDMA Base Station and Cell Site Controller.
Combined Processor and Time Switch boards while increasing performance with Motorola 68040 and High Speed Memory. Responsible for the Firmware drivers, system timing synchronization to T1 and worked with the hardware designers as advisor to integrate, review the design and provide suggestion and design problem solving.
Designed diagnostics software to test 68040 Processor interface CPLD and assist hardware designers to provide hardware design changes to fix problems and enhance the performance and increase the quality of the product.
Part of the design team to implement dual bank field upgradeable Firmware using the EEPROMs and Lattice CPLD.
Contributed to the design team to ensured Hot-Insertion of Circuit Board in redundant system, embedded hardware assist diagnostics test circuit, Increase hardware test capability by providing loop back control and test registers in the data path.
Enhance Time Switch redesign technical advisor to add new features
Team leader for the DSPM hardware design team. Contribute in the system, architecture, hardware and software design, verification and field issue debugging of the TDMA MSC, BSC, BTS, analog and digital dual mode radio(DRU).
Responsible for the TDMA Base Station Controller Product specification.
Blu Box Fraud Detection using BitSlice DSP (1987 support up to 2003)
Responsible for redesign of the DSP filters and firmware for a 480 channel SF, MF and DTMF tone receiver for re-origination and Blue Box Fraud Detection feature in the long distance carrier switch (DMS-250).
Responsible for redesign of the Motorola 68HC000 processor firmware and software. (68000 assembly, BNR Pascal, Protel, Micro kernel).
Re-design the firmware and software to improve real-time, capacity and verify the design for all the time domain and frequency domain specification and speech talk off specification.
Hardware debugging, prototyping and support. Design change, release documentation, library firmware and software release process.
CMC Message Processor Firmware design (1987-1988)
Micro code firmware design for the CMC message processor connecting the DMS-250 (switch for the long distance service provider) DS30 link (2.5 Mb links) with redundancy link to connect billing server to the DMS-250.
Also responsible for hardware, software and designer system testing and debugging.
Specialized Tone Receiver using BitSlice DSP (STR) (1987 support up to 2003)
Responsible for the DSP (AMD 2909 Sequencer, 2900 bitslice ALU) daughter board Hardware and Microcode firmware implementing digital filters for a 480 channel DTMF tone receiver for re-origination feature in the long distance carrier switch (DMS-250).
Design team member for the mother board using the Motorola 68HC000 processor to implement control system, messaging and diagnostics, fault recovery.
Firmware design specification and test specification for speech talk off testing of the DTMF receiver sensitivity during the speech or music or background noise.
Setup in house meta assembler and define the 48 bits DSP board instructions.
Design Prime for the firmware, implementing the DSP time domain processing of PCM speech samples, diagnostics code, messaging and all the drivers.
Hardware debugging, prototyping and support. Design change and release documentation.
Meridian SL-100 and DMS-100 Disk Subsystem Design (1985-1986 support up to 2003)
Responsible for disk subsystem and controller hardware and microcode firmware design and packaging for the Cellular MTX, DMS-100,250,500, MSL-100.
Design Prime for Disk subsystem and controller product and commercial specification, Hardware, software and system diagnostics, utility and messaging.
Design Prime for the disk controller Firmware design (Microcode, Bit slice 2900 family design, Priam disk interface and NT SCIS disk interface).
Cost reduces the product by %83.
Danray CTSS4K, 1K, RSS250, PBX, Data switch Hardware Design Support (1982-1985)
Responsible for hardware design modification to the existing circuit packs for the listed telephone switches.
Design modification to the Memory expansion boxes for the Nova 3 and Point 4 mini computer.
Resolve field issues and provided hardware, software design solution for the Intercel, Mostak memory expansion boxes
Hardware design modification to circuit packs in the Danray switches, Memory and CPU interface, speech synthesis, DTMF, MF sender, receiver, subsystem interfaces, 2 wires, 4 wire trunk interface card, disk controller and more.
Danray and Nortel Manufacture System Staging and Testing (1981-1982.5)
Responsible for the system staging, database configuration, testing and repair.
Test, debug and fix wiring, shelf and subsystem problems for the PBX, CTSS4k,1K.
Graduated from Devry University with BSEET degree.
Danray and Nortel Manufacture PC Board Testing and Repair (1980-1981)
Responsible for the testing and debugging of all the circuit packs used in the Danray telephone switches.
Test debug and fix PC board problems using custom made tester modules and automated test equipment.
Attend Devry University as a full time student seeking BSEET degree and working full time in the manufacturing at night.
TV and Radio repair Electronics Technician (1973-1975)
Part time repair Radio and TV during high school and summer.
Electronic Technician (1973-1975)
Design and repair of the power circuits and the electrical wiring. Building and repair motors, Alternators, Transformers and power distribution equipment design and repair. Part time during my technical high school years. (Last 3 years, technical high school)
EDUCATION
BSEET, Electronics Engineering Technology, Devry University, Irving, Texas (1982)
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